But they're still, as far as I've seen, terrible at debugging HDL. There's just too many interconnected signals. Blocking vs nonblocking assignments and scoping are very hard for it. But I have yet to try opus 5.5 on it.
Agreed. You have to give them device-in-the-loop with trace or a decent simulator. Presumably the big EDA companies are working on tooling integration and bespoke models, and they have huge libraries of designs to draw on.
Yeah I have yet to get it to close the loop. I have some stuff theorized but everything else ends up in the way. Last time it got stuck going to the open internet because obviously I'm not letting it do that but it wouldn't stop trying. I just gave up after that. But once I can close the loop, I have big plans.